AMD's Venice is the first 2nm x86 server chip, but the stack doesn't fully ship until 2027
Pro AMD's Venice is the first 2nm x86 server chip, but the stack doesn't fully ship until 2027 News By Rahim Amir Published 27 July 2026 More cores and more threads for the data center When you purchase through links on our site, we may earn an affiliate commission. You will receive a confirmation email shortly."},"failureMessage":"There was a problem. Follow TechRadar on Google News and add us as a preferred source to get our expert news, reviews, and opinion in your feeds.
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| Original publisher | TechRadar |
| Canonical URL | https://www.techradar.com/pro/amds-venice-is-the-first-2nm-x86-server-chip-but-the-stack-doesnt-fully-ship-until-2027 |
| Publication time | Mon, 27 Jul 2026 21:40:00 +0000 |
| Retrieval time | 2026-07-27T21:43:28.362Z |
| Last seen | 2026-07-27T21:43:28.362Z |
| Headline source | Publisher (no WeSearch rewrite) |
| Excerpt source | publisher body |
| Excerpt method | First ~120 words (~800 chars) of extracted publisher body, fair-use limited. |
| Summary | WeSearch · cerebras-chat (WeSearch summarizer) |
| Summary source text | contentText |
| Citation coverage | Summary is a WeSearch-generated derivative; primary citation is the original publisher URL. |
| Cluster | bv8NLAMh_S0d · 1 stories |
| Cluster logic | Grouped by semantic title/content similarity across sources within a rolling window. Same-publisher template collisions are excluded from coverage comparison. |
| Ranking reason | Story pages are not engagement-ranked. Hub feeds use recency, with optional source-diversified chronological ordering (cap consecutive stories per source). No personalized ranking. |
| Publisher visit | Yes — open original |
| Substitutes article? | No — link-out required for full text |
Rights status (four layers)
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| Indexing | May the item be indexed (stored, ranked, made findable)? | Allowed |
| Snippet | May a short excerpt of the publisher's text be shown? | Allowed |
| AI summary | May WeSearch generate its own short summary of the article? | Limited |
| Retrieval / RAG | May the content be exposed for third-party retrieval-augmented generation? | Not asserted |
| Model training | May the content be used to train AI models? | Not asserted |
| Commercial reuse | May the content be reused commercially? | Not permitted |
Basis: Derived from the published RSS/Atom feed. Contact: [email protected]. Reviewed: 2026-07-24.
Opening excerpt (first ~120 words) tap to expand
Pro AMD's Venice is the first 2nm x86 server chip, but the stack doesn't fully ship until 2027 News By Rahim Amir Published 27 July 2026 More cores and more threads for the data center When you purchase through links on our site, we may earn an affiliate commission. Here’s how it works. (Image credit: AMD) Copy link Facebook X Whatsapp Reddit Pinterest Flipboard Threads Email Share this article 0 Join the conversation Follow us Add us as a preferred source on Google Newsletter Subscribe to our newsletter AMD EPYC 9006 "Venice" offers mammoth 256-core, 512-thread configuration that incorporates up to 1GB of L3 cache and PCI-E 6.0 and 16 DDR5 memory channels under the hoodIt's the first time AMD's EPYC lineup sees high core count CPUs push past the 5GHz barrierAMD is claiming a win by…
Excerpt limited to ~120 words for fair-use compliance. The full article is at TechRadar.
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