Hardware backdoors in some x86 CPUs
Researchers have identified a hardware backdoor embedded in certain VIA C3 x86 processors that can bypass protection mechanisms to access kernel memory. The backdoor may be enabled by default on some systems, allowing unprivileged code to read and write ring 0 data. Tools are provided to detect and partially mitigate the issue, though they are experimental and limited to older CPU generations.
- ▪The backdoor consists of a hidden core alongside the main x86 core, activated via a model‑specific register and a launch instruction.
- ▪It can allow user‑level code to modify kernel memory without requiring kernel privileges.
- ▪The vulnerability appears to affect only VIA C3 CPUs, with later generations lacking the feature.
- ▪Researchers released utilities to check for the backdoor and scripts to attempt to disable it during boot, but they may be unstable.
- ▪The work is presented as a case study on how complex processor designs can harbor undisclosed capabilities.
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| Original publisher | GitHub |
| Canonical URL | https://github.com/xoreaxeaxeax/rosenbridge |
| Publication time | Sat, 08 Aug 2026 07:04:51 +0000 |
| Retrieval time | 2026-08-08T07:50:41.767Z |
| Last seen | 2026-08-08T07:50:41.767Z |
| Headline source | Publisher (no WeSearch rewrite) |
| Excerpt source | publisher body |
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| Summary | WeSearch · cerebras-chat (WeSearch summarizer) |
| Summary source text | contentText |
| Citation coverage | Summary is a WeSearch-generated derivative; primary citation is the original publisher URL. |
| Cluster | uarU3mynemFd · 1 stories |
| Cluster logic | Grouped by semantic title/content similarity across sources within a rolling window. Same-publisher template collisions are excluded from coverage comparison. |
| Ranking reason | Story pages are not engagement-ranked. Hub feeds use recency, with optional source-diversified chronological ordering (cap consecutive stories per source). No personalized ranking. |
| Publisher visit | Yes — open original |
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| Retrieval / RAG | May the content be exposed for third-party retrieval-augmented generation? | Not asserted |
| Model training | May the content be used to train AI models? | Not asserted |
| Commercial reuse | May the content be reused commercially? | Not permitted |
Basis: Derived from the published RSS/Atom feed. Contact: [email protected]. Reviewed: 2026-07-24.
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project:rosenbridge : hardware backdoors in x86 CPUs github.com/xoreaxeaxeax/rosenbridge // domas // @xoreaxeaxeax Overview project:rosenbridge reveals a hardware backdoor in some desktop, laptop, and embedded x86 processors. The backdoor allows ring 3 (userland) code to circumvent processor protections to freely read and write ring 0 (kernel) data. While the backdoor is typically disabled (requiring ring 0 execution to enable it), we have found that it is enabled by default on some systems. This repository contains utilities to check if your processor is affected, close the backdoor if it is present, and the research and tools used to discover and analyze the backdoor. The Backdoor The rosenbridge backdoor is a small, non-x86 core embedded alongside the main x86 core in the CPU.
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Excerpt limited to ~120 words for fair-use compliance. The full article is at GitHub.