High Speed Networking: The View from the Machine
The article discusses the mechanisms that enable high-speed Networking Interface Cards (NICs) to communicate with CPUs. It outlines the role of PCIe in connecting high-bandwidth devices and the importance of memory management techniques like MMIO. Additionally, it explains how data flows through the system to achieve optimal performance.
- ▪High-speed NICs operate at speeds of 10GbE, 100GbE, or higher by leveraging advanced hardware mechanisms.
- ▪PCIe connects high-bandwidth devices to the CPU, allowing for efficient communication through dedicated lanes.
- ▪MMIO allows the CPU to interact with I/O device registers using the same physical address space as main memory.
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High Speed Networking: The View from the MachineMay 22, 2026 · 14 minTable of ContentsMMIO (Memory Mapped I/O)The MMIO Access FlowDMA (Direct Memory Access)IOMMU (I/O Memory Management Unit)Intel DDIO (Data Direct I/O)PCIe TPH and Steering TagsSMART DATA CACHE INJECTION (AMD SDCI)NICsThe Flow: Receive & TransmitFurther ReadingThis series of articles explores how I/O devices communicate with the CPU and the hardware mechanisms that enable high-speed Networking Interface Cards (NICs) to operate at 10GbE, 100GbE, or higher. In this article, we’re going to trace the physical and micro-architectural paths a packet takes from the wire to an application.
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Excerpt limited to ~120 words for fair-use compliance. The full article is at C21 Blog.
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