Huawei plans to narrow semiconductor gap with TSMC using novel chip architecture
Huawei has announced plans to reduce the semiconductor technology gap with TSMC by introducing new chip architecture. The company aims to achieve 1.4-nanometer chip density by 2031 using its proprietary Tau Scaling Law and LogicFolding technology. This approach seeks to circumvent the limitations imposed by US sanctions on advanced lithography machines.
- ▪Huawei unveiled its new scaling framework and LogicFolding technology at the IEEE International Symposium on Circuits and Systems in Shanghai.
- ▪The company plans to achieve transistor density equivalent to 1.4-nanometer chips by 2031, three years later than TSMC's target of 2028.
- ▪Huawei has already mass-produced 381 chips based on these new principles over the past six years.
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Huawei plans to narrow semiconductor gap with TSMC using novel chip architecture The Chinese tech giant unveiled a new scaling framework and LogicFolding technology aimed at matching 1.4-nanometer chip density by 2031, without needing the advanced lithography machines US sanctions have blocked. Share Add us on Google by Editorial Team May. 29, 2026 window.sevioads = window.sevioads || []; var sevioads_preferences = []; sevioads_preferences[0] = {}; sevioads_preferences[0].zone = "01f21ccf-2092-46b1-9ac7-8c44cc782e0f"; sevioads_preferences[0].adType = "native"; sevioads_preferences[0].inventoryId = "c5700508-581b-472c-8fdd-a931cdbfc8e1"; sevioads_preferences[0].accountId = "1e47efc1-ec2d-4fca-a8b9-354e249e5095"; sevioads.push(sevioads_preferences); Huawei just told the world it plans to…
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