LoopLynx: A Scalable Dataflow Architecture for Efficient LLM Inference
LoopLynx is a scalable dataflow architecture designed to improve large language model (LLM) inference on FPGA platforms. It combines a hybrid spatial‑temporal design with a multi‑FPGA distributed system that hides data transfers to maximize utilization. Benchmarks on GPT‑2 show performance comparable to state‑of‑the‑art single‑FPGA solutions and a 2.52× latency improvement over an Nvidia A100 while using less than half the energy.
- ▪LoopLynx uses a hybrid spatial‑temporal architecture where intensive operators are implemented as large dataflow kernels, achieving high throughput.
- ▪The design organizes and reuses these kernels temporally to enhance FPGA peak performance.
- ▪A multi‑FPGA distributed architecture overlaps and hides all data transfers, enabling effective scaling for large‑scale LLM inference.
- ▪Compared to an Nvidia A100, a dual‑FPGA configuration of LoopLynx delivers a 2.52× speed‑up in inference latency while consuming only 48.1% of the energy.
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| Original publisher | arXiv.org |
| Canonical URL | https://arxiv.org/abs/2504.09561 |
| Publication time | Tue, 28 Jul 2026 10:33:09 +0000 |
| Retrieval time | 2026-07-28T10:59:35.201Z |
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Computer Science > Hardware Architecture arXiv:2504.09561 (cs) [Submitted on 13 Apr 2025] Title:LoopLynx: A Scalable Dataflow Architecture for Efficient LLM Inference Authors:Jianing Zheng, Gang Chen View a PDF of the paper titled LoopLynx: A Scalable Dataflow Architecture for Efficient LLM Inference, by Jianing Zheng and Gang Chen View PDF HTML (experimental) Abstract:In this paper, we propose LoopLynx, a scalable dataflow architecture for efficient LLM inference that optimizes FPGA usage through a hybrid spatial-temporal design. The design of LoopLynx incorporates a hybrid temporal-spatial architecture, where computationally intensive operators are implemented as large dataflow kernels.
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