Monte Cimone v3: Where RISC-V Stands in High-Performance Computing
The Monte Cimone v3 project introduces a RISC-V testbed for high-performance computing. This iteration integrates the advanced SOPHGO Sophon SG2044 processor, significantly enhancing performance and energy efficiency. The results indicate that MCv3 achieves competitive performance metrics compared to established platforms like Intel and NVIDIA.
- ▪Monte Cimone v3 (MCv3) is the third iteration of a RISC-V HPC cluster.
- ▪The SG2044 processor used in MCv3 more than doubles single-core performance compared to its predecessor.
- ▪MCv3 achieves an energy efficiency of 3.08GFLOPs/W, improving 10x over the previous version.
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Computer Science > Distributed, Parallel, and Cluster Computing arXiv:2605.22831 (cs) [Submitted on 22 Apr 2026] Title:Monte Cimone v3: Where RISC-V Stands in High-Performance Computing Authors:Emanuele Venieri, Simone Manoni, Giacomo Madella, Federico Proverbio, Federico Ficarelli, Luca Benini, Andrea Bartolini View a PDF of the paper titled Monte Cimone v3: Where RISC-V Stands in High-Performance Computing, by Emanuele Venieri and 5 other authors View PDF HTML (experimental) Abstract:The Monte Cimone project provides a RISC-V testbed for High-Performacne Computing cluster. This paper presents Monte Cimone v3 (MCv3), the third iteration of the Monte Cimone RISC-V HPC cluster, integrating the SOPHGO Sophon SG2044 processor, an evolution of the SG2042 used in MCv2.
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