TSMC’s latest chip packaging breakthrough promises lower costs and better performance
Making chips smaller has dominated the semiconductor conversation for years, but TSMC’s next big leap may come from how those chips are packaged instead. According to analyst Ming-Chi Kuo, the company is developing a new Chip-on-Panel-on-Substrate, or CoPoS, technology that promises lower manufacturing costs while delivering better performance for future AI processors. TSMC’s CoPoS packaging could make future AI chips both cheaper and faster In a recent post on X, Ming-Chi Kuo revealed that TSMC is working on CoPoS, an advanced packaging architecture that replaces conventional wafer-based manufacturing with panel-level processing.
- ▪Making chips smaller has dominated the semiconductor conversation for years, but TSMC’s next big leap may come from how those chips are packaged instead.
- ▪According to analyst Ming-Chi Kuo, the company is developing a new Chip-on-Panel-on-Substrate, or CoPoS, technology that promises lower manufacturing costs while delivering better performance for future AI processors.
- ▪TSMC’s CoPoS packaging could make future AI chips both cheaper and faster In a recent post on X, Ming-Chi Kuo revealed that TSMC is working on CoPoS, an advanced packaging architecture that replaces conventional wafer-based manufacturing wi
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| Original publisher | Digital Trends |
| Canonical URL | https://www.digitaltrends.com/computing/tsmcs-latest-chip-packaging-breakthrough-promises-lower-costs-and-better-performance/ |
| Publication time | Sun, 14 Jun 2026 21:29:26 +0000 |
| Retrieval time | 2026-06-14T22:13:02.798Z |
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Making chips smaller has dominated the semiconductor conversation for years, but TSMC’s next big leap may come from how those chips are packaged instead. According to analyst Ming-Chi Kuo, the company is developing a new Chip-on-Panel-on-Substrate, or CoPoS, technology that promises lower manufacturing costs while delivering better performance for future AI processors. TSMC’s CoPoS packaging could make future AI chips both cheaper and faster In a recent post on X, Ming-Chi Kuo revealed that TSMC is working on CoPoS, an advanced packaging architecture that replaces conventional wafer-based manufacturing with panel-level processing.
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Excerpt limited to ~120 words for fair-use compliance. The full article is at Digital Trends.
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