Veryl Simulator: Performance Comparison with Verilator
The Veryl simulator has been compared to Verilator, revealing performance advantages in both first-run and cached scenarios. Veryl's Cranelift backend allows for quicker initial execution, while its GCC backend optimizes performance during longer simulations. Future developments will expand benchmarking across different CPU architectures and designs.
- ▪The Veryl simulator combines Cranelift and GCC backends for optimized performance.
- ▪In first-run tests, Veryl outperformed Verilator by 33% to 61% across different machines.
- ▪On cached runs, Veryl remained faster than Verilator, especially on older CPU architectures.
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| Original publisher | Veryl-lang |
| Canonical URL | https://veryl-lang.org/blog/veryl-simulator-performance/ |
| Publication time | Tue, 26 May 2026 12:57:10 +0000 |
| Retrieval time | 2026-05-26T13:07:49.469Z |
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Approach Benchmark Observations What's next Veryl Simulator: Performance Comparison with Verilator 2026-05-26 We have been working on a native Veryl simulator built on the new IR-based analyzer introduced earlier this year. This post shares early performance numbers comparing it against Verilator, the de facto standard open source SystemVerilog simulator. Approach The Veryl simulator combines two execution backends: A Cranelift-based backend that trades optimization quality for compile speed, so the first run starts with little upfront cost. A GCC-based backend that runs in the background to produce a more heavily optimized binary. Once the optimized binary is ready, the running simulation switches over to it dynamically.
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