Mysterious 16-Tile & 32-Tile AMX Implementations Talked Up For More Performance
Mysterious 16-Tile & 32-Tile AMX Implementations Talked Up For More Performance Written by Michael Larabel in Hardware on 27 July 2026 at 12:41 PM EDT. Add A Comment Last October on Phoronix we were first to point out there being some mysterious intrigue around a new x86 implementation from a "corporate entity other than Intel/AMD" with the developer involved not elaborating on the matter. Now that same developer has posted another semi-cryptic message to the Linux kernel mailing list to talk about 16-tile and 32-tile Advanced Matrix Extensions (AMX) implementations.
- ▪Mysterious 16-Tile & 32-Tile AMX Implementations Talked Up For More Performance Written by Michael Larabel in Hardware on 27 July 2026 at 12:41 PM EDT.
- ▪Add A Comment Last October on Phoronix we were first to point out there being some mysterious intrigue around a new x86 implementation from a "corporate entity other than Intel/AMD" with the developer involved not elaborating on the matter.
- ▪Now that same developer has posted another semi-cryptic message to the Linux kernel mailing list to talk about 16-tile and 32-tile Advanced Matrix Extensions (AMX) implementations.
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Record
| Original publisher | Phoronix |
| Canonical URL | https://www.phoronix.com/news/16-Tile-32-Tile-AMX-Performance |
| Publication time | Mon, 27 Jul 2026 12:41:37 -0400 |
| Retrieval time | 2026-07-27T16:46:27.638Z |
| Last seen | 2026-07-27T16:46:27.638Z |
| Headline source | Publisher (no WeSearch rewrite) |
| Excerpt source | publisher body |
| Excerpt method | First ~120 words (~800 chars) of extracted publisher body, fair-use limited. |
| Summary | WeSearch · cerebras-chat (WeSearch summarizer) |
| Summary source text | contentText |
| Citation coverage | Summary is a WeSearch-generated derivative; primary citation is the original publisher URL. |
| Cluster | ignzR2HDsWjR · 1 stories |
| Cluster logic | Grouped by semantic title/content similarity across sources within a rolling window. Same-publisher template collisions are excluded from coverage comparison. |
| Ranking reason | Story pages are not engagement-ranked. Hub feeds use recency, with optional source-diversified chronological ordering (cap consecutive stories per source). No personalized ranking. |
| Publisher visit | Yes — open original |
| Substitutes article? | No — link-out required for full text |
Rights status (four layers)
WeSearch handling by dimension
| Indexing | May the item be indexed (stored, ranked, made findable)? | Allowed |
| Snippet | May a short excerpt of the publisher's text be shown? | Allowed |
| AI summary | May WeSearch generate its own short summary of the article? | Limited |
| Retrieval / RAG | May the content be exposed for third-party retrieval-augmented generation? | Not asserted |
| Model training | May the content be used to train AI models? | Not asserted |
| Commercial reuse | May the content be reused commercially? | Not permitted |
Basis: Derived from the published RSS/Atom feed. Contact: [email protected]. Reviewed: 2026-07-24.
Opening excerpt (first ~120 words) tap to expand
Mysterious 16-Tile & 32-Tile AMX Implementations Talked Up For More Performance Written by Michael Larabel in Hardware on 27 July 2026 at 12:41 PM EDT. Add A Comment Last October on Phoronix we were first to point out there being some mysterious intrigue around a new x86 implementation from a "corporate entity other than Intel/AMD" with the developer involved not elaborating on the matter. Now that same developer has posted another semi-cryptic message to the Linux kernel mailing list to talk about 16-tile and 32-tile Advanced Matrix Extensions (AMX) implementations. To date Intel only has 8-tile AMX. Christian Ludloff has in the past has worked for Google, AMD, TI, and others as an x86 architecture expert and maintainer of the Sandpile.org x86 CPU information site.
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Excerpt limited to ~120 words for fair-use compliance. The full article is at Phoronix.