Xezim – a Rust-based SystemVerilog simulator
Xezim is a lightweight SystemVerilog simulator developed in Rust, aimed at simplifying chip design workflows. The project seeks to determine if a small team or individual can create essential EDA tools with AI assistance. Current features include parsing SystemVerilog code, simulating combinational and sequential logic, and generating waveform dumps.
- ▪Xezim was previously known as sisSIM and has undergone renaming without changing its behavior.
- ▪The simulator is designed for experimentation and learning in AI-assisted chip design.
- ▪It includes capabilities such as module parsing, signal representation, and a test execution framework.
Opening excerpt (first ~120 words) tap to expand
xezim — SystemVerilog Simulator (Rust) xezim is a lightweight SystemVerilog simulator written in Rust designed for experimentation, learning, and exploring AI-assisted chip design workflows. xezim was previously developed under the name sisSIM. The binary, library, and compiled-artifact magic were renamed in place; behavior is unchanged. This project explores whether modern tools and AI can dramatically reduce the complexity of building core EDA infrastructure such as simulators. The simulator parses SystemVerilog source code, builds an internal representation, and executes simulations for combinational and sequential logic. Motivation Traditional EDA tools require very large engineering teams and many years of development.
…
Excerpt limited to ~120 words for fair-use compliance. The full article is at GitHub.